1. Field of the Invention
The present invention relates to an image display device, and is applicable to an active matrix type image display device using Jun. 2, 2008 (Electro Luminescence) element, for example. The present invention disposes a switch transistor between a driving transistor and a light emitting element, and sets the switch transistor in an off state during non-emission periods, whereby variation in threshold voltage of the driving transistor is corrected while destruction of the light emitting element due to a reverse bias is effectively avoided.
2. Description of the Related Art
In related art, an active matrix type image display device using an organic EL element has a display section formed by arranging pixel circuits each formed by the organic EL element and a driving circuit for driving the organic EL element in the form of a matrix. The image display device of this type has each pixel formed by an organic EL element provided in the pixel circuit, and drives each pixel circuit by a signal line driving circuit and a scanning line driving circuit arranged on the periphery of the display section to display a desired image.
In relation to the image display device using the organic EL element, Japanese Patent Laid-Open No. 2007-310311 (hereinafter referred to as Patent Document 1) discloses a method of forming a pixel circuit using two transistors. Thus, according to the method disclosed in Patent Document 1, a constitution can be simplified. Patent Document 1 also discloses a constitution for correcting a variation in threshold voltage and a variation in mobility of a driving transistor driving an organic EL element. Thus, according to the constitution disclosed in Patent Document 1, degradation in image quality due to a variation in threshold voltage and a variation in mobility of the driving transistor can be prevented.
FIG. 10 is a block diagram showing the image display device disclosed in Patent Document 1. The image display device 1 has a display section 2 created on an insulating substrate of glass or the like. The image display device 1 has a signal line driving circuit 3 and a scanning line driving circuit 4 created on the periphery of the display section 2.
The display section 2 is formed by arranging pixel circuits 5 in the form of a matrix, and pixels (PIX) 6 are formed by organic EL elements provided in the pixel circuits 5. Incidentally, in an image display device for color images, one pixel is formed by a plurality of sub-pixels of red, green, and blue. Thus, in the case of the image display device for color images, the display section 2 is formed by sequentially arranging pixel circuits 5 for red, green, and blue forming sub-pixels of red, green, and blue, respectively.
The signal line driving circuit 3 outputs driving signals Ssig for signal lines to signal lines DTL provided in the display section 2. More specifically, a data scan circuit 3A in the signal line driving circuit 3 distributes image data D1 input in the order of raster scanning to the signal lines DTL by sequentially latching the image data D1, and thereafter subjects each piece of the distributed image data D1 to a digital-to-analog conversion process. The signal line driving circuit 3 processes a result of the digital-to-analog conversion, and generates the driving signals Ssig. The image display device 1 thereby sets a gradation of each pixel circuit 5 on a so-called line-sequential basis, for example.
The scanning line driving circuit 4 outputs a writing signal WS and a driving signal DS to scanning lines WSL for writing signals and scanning lines DSL for power supply, respectively, the scanning lines WSL and the scanning lines DSL being provided in the display section 2. The writing signal WS is a signal for performing on-off control on a writing transistor provided in each pixel circuit 5. The driving signal DS is a signal for controlling the drain voltage of a driving transistor provided in each pixel circuit 5. A write scan circuit (WSCN) 4A and a drive scan circuit (DSCN) 4B in the scanning line driving circuit 4 each process a predetermined sampling pulse SP with a clock CK to generate the writing signal WS and the driving signal DS.
FIG. 11 is a connection diagram showing details of a configuration of a pixel circuit 5. In the pixel circuit 5, the cathode of an organic EL element 8 is set at a predetermined negative side voltage. In the example of FIG. 11, the negative side voltage is set at the voltage of a ground line. In the pixel circuit 5, the anode of the organic EL element 8 is connected to the source of a driving transistor Tr2. Incidentally, the driving transistor Tr2 is an N-channel type transistor formed by a TFT, for example. In the pixel circuit 5, the drain of the driving transistor Tr2 is connected to a scanning line DSL for power supply, and a driving signal DS for power supply is supplied from the scanning line driving circuit 4 to the scanning line DSL. Thus, the pixel circuit 5 current-drives the organic EL element 8 using the driving transistor Tr2 of a source follower circuit configuration.
The pixel circuit 5 has a storage capacitor Cs between the gate and the source of the driving transistor Tr2. The gate side terminal voltage of the storage capacitor Cs is set at the voltage of a driving signal Ssig by a writing signal WS. As a result, the pixel circuit 5 current-drives the organic EL element 8 by the driving transistor Tr2 according to a gate-to-source voltage Vgs corresponding to the driving signal Ssig. Incidentally, in FIG. 11, a capacitance Cel is a stray capacitance of the organic EL element 8. Suppose in the following that the capacitance Cel is sufficiently larger than the capacitance of the storage capacitor Cs, and that the parasitic capacitance of the gate node of the driving transistor Tr2 is sufficiently smaller than the capacitance of the storage capacitor Cs.
In the pixel circuit 5, the gate of the driving transistor Tr2 is connected to a signal line DTL via a writing transistor Tr1, which performs on-off operation according to the writing signal WS. Incidentally, in this case, the writing transistor Tr1 is an N-channel type transistor formed by a TFT, for example. In this case, the signal line driving circuit 3 outputs the driving signal Ssig by selecting a gradation setting voltage Vsig and a voltage Vofs for threshold voltage correction in predetermined timing. In this case, the fixed voltage Vofs for threshold voltage correction is a fixed voltage used to correct a variation in threshold voltage of the driving transistor Tr2. The gradation setting voltage Vsig is a voltage indicating the light emission luminance of the organic EL element 8, and is a voltage obtained by adding the fixed voltage Vofs for threshold voltage correction to a gradation voltage Vin. The gradation voltage Vin is a voltage corresponding to the light emission luminance of the organic EL element 8. The gradation voltage Vin is generated for each signal line DTL by subjecting each piece of image data D1 distributed to each signal line DTL to a digital-to-analog conversion process.
In the pixel circuit 5, as shown in FIGS. 12A to 12E, the writing transistor Tr1 is set in an off state by the writing signal WS during an emission period during which the organic EL element 8 is made to emit light (FIG. 12A). In the pixel circuit 5, during the emission period, a power supply voltage Vcc is supplied to the driving transistor Tr2 by the driving signal DS for power supply (FIG. 12B). As shown in FIG. 13, the pixel circuit 5 thereby makes the organic EL element 8 emit light by a driving current Ids corresponding to the gate-to-source voltage Vgs (FIGS. 12D and 12E) of the driving transistor Tr2, which voltage is a voltage across the storage capacitor Cs, during the emission period.
In the pixel circuit 5, the driving signal DS for power supply is lowered to a predetermined fixed voltage Vss at time t0 at which the emission period ends (FIG. 12B). The fixed voltage Vss is a voltage low enough to make the drain of the driving transistor Tr2 function as a source, and is a voltage lower than the cathode voltage of the organic EL element 8.
Thereby, in the pixel circuit 5, as shown in FIG. 14, an accumulated charge of the terminal on the organic EL element 8 side of the storage capacitor Cs flows out to the scanning line via the driving transistor Tr2. As a result, in the pixel circuit 5, the source voltage Vs of the driving transistor Tr2 is lowered to the voltage Vss (FIG. 12E), and the organic EL element 8 stops emitting light. In addition, in the pixel circuit 5, the gate voltage Vg of the driving transistor Tr2 is lowered in such a manner as to be interlocked with the lowering of the source voltage Vs (FIG. 12D).
Incidentally, to be more exact, due to the lowering of the drain voltage to the fixed voltage Vss, the gate voltage Vg of the driving transistor Tr2 is maintained at a voltage lowered from the fixed voltage Vss by the threshold voltage of the drain-to-gate voltage of the driving transistor Tr2. The source voltage Vs of the driving transistor Tr2 is maintained at a voltage lowered from the gate voltage Vg by a gate-to-source voltage in an immediately preceding emission period.
In the pixel circuit 5, at a predetermined next time t1, the writing transistor Tr1 is changed to an on state by the writing signal WS (FIG. 12A), and the gate voltage Vg of the driving transistor Tr2 is set at the fixed voltage Vofs for threshold voltage correction which voltage Vofs is set in the signal line DTL (FIGS. 12C and 12D). Thereby, in the pixel circuit 5, as shown in FIG. 15, the gate-to-source voltage Vgs of the driving transistor Tr2 is set at substantially a voltage Vofs-Vss. In the pixel circuit 5, due to the settings of the voltages Vofs and Vss, the voltage Vofs-Vss is set to a voltage larger than the threshold voltage Vth of the driving transistor Tr2.
Thereafter, in the pixel circuit 5, the drain voltage of the driving transistor Tr2 is raised to a power supply voltage Vcc by the driving signal DS at time t2 (FIG. 12B). Thereby, in the pixel circuit 5, as shown in FIG. 16, a charging current Ids flows in from the power supply Vcc to the terminal on the organic EL element 8 side of the storage capacitor Cs via the driving transistor Tr2. As a result, in the pixel circuit 5, the voltage Vs of the terminal on the organic EL element 8 side of the storage capacitor Cs rises gradually. Incidentally, in this case, in the pixel circuit 5, the current Ids flowing into the organic EL element 8 via the driving transistor Tr2 is used only to charge the capacitance Cel of the organic EL element 8 and the storage capacitor Cs. As a result, only the source voltage Vs of the driving transistor Tr2 rises without the organic EL element 8 emitting light.
In the pixel circuit 5, when the voltage across the storage capacitor Cs becomes the threshold voltage Vth of the driving transistor Tr2, the charging current Ids stops flowing in via the driving transistor Tr2. Thus, in this case, the source voltage Vs of the driving transistor Tr2 stops rising when the voltage across the storage capacitor Cs becomes the threshold voltage Vth of the driving transistor Tr2. The pixel circuit 5 thereby discharges the voltage across the storage capacitor Cs via the driving transistor Tr2, and sets the voltage across the storage capacitor Cs to the threshold voltage Vth of the driving transistor Tr2.
In the pixel circuit 5, at time t3 after the passage of a sufficient time to set the voltage across the storage capacitor Cs to the threshold voltage Vth of the driving transistor Tr2, as shown in FIG. 17, the writing transistor Tr1 is changed to an off state by the writing signal WS (FIG. 12A). Next, as shown in FIG. 18, the voltage of the signal line DTL is set to the gradation setting voltage Vsig (=Vin+Vofs).
In the pixel circuit 5, the writing transistor Tr1 is set in an on state at next time t4 (FIG. 12A). Thereby, in the pixel circuit 5, as shown in FIG. 19, the gate voltage Vg of the driving transistor Tr2 is set at the gradation setting voltage Vsig, and the gate-to-source voltage Vgs of the driving transistor Tr2 is set at a voltage obtained by adding the threshold voltage Vth of the driving transistor Tr2 to a gradation voltage Vin. Thereby, the pixel circuit 5 can drive the organic EL element 8 while effectively avoiding a variation in threshold voltage Vth of the driving transistor Tr2, and thus prevent degradation in image quality due to a variation in light emission luminance of the organic EL element 8.
In the pixel circuit 5, at the time of setting the gate voltage Vg of the driving transistor Tr2 to the gradation setting voltage Vsig, the gate of the driving transistor Tr2 is connected to the signal line DTL for a certain period with the drain voltage of the driving transistor Tr2 maintained at the power supply voltage Vcc. Thereby the pixel circuit 5 also corrects a variation in mobility μ of the driving transistor Tr2.
That is, when the gate of the driving transistor Tr2 is connected to the signal line DTL by setting the writing transistor Tr1 in an on state with the voltage across the storage capacitor Cs set to the threshold voltage Vth of the driving transistor Tr2, the gate voltage Vg of the driving transistor Tr2 gradually rises from the fixed voltage Vofs and is set to the gradation setting voltage Vsig.
In the pixel circuit 5, a writing time constant necessary for the rising of the gate voltage Vg of the driving transistor Tr2 is set shorter than a time constant necessary for the rising of the source voltage Vs of the driving transistor Tr2.
In this case, when the writing transistor Tr1 performs an on operation, the gate voltage Vg of the driving transistor Tr2 quickly rises to the gradation setting voltage Vsig (Vofs+Vin). At the time of the rising of the gate voltage Vg, when the capacitance Cel of the organic EL element 8 is sufficiently larger than the capacitance of the storage capacitor Cs, the source voltage Vs of the driving transistor Tr2 does not vary.
However, when the gate-to-source voltage Vgs of the driving transistor Tr2 becomes larger than the threshold voltage Vth, the current Ids flows in from the power supply Vcc via the driving transistor Tr2, and the source voltage Vs of the driving transistor Tr2 rises gradually. As a result, in the pixel circuit 5, the voltage across the storage capacitor Cs is discharged by the driving transistor Tr2, and the rising speed of the gate-to-source voltage Vgs is lowered.
The discharging speed of the voltage across the storage capacitor Cs changes according to the capability of the driving transistor Tr2. More specifically, the higher the mobility μ of the driving transistor Tr2, the faster the discharging speed.
As a result, in the pixel circuit 5, the higher the mobility μ of the driving transistor Tr2, the lower the voltage across the storage capacitor Cs, whereby a variation in light emission luminance due to a variation in mobility is corrected. Incidentally, an amount of decrease in the voltage across the storage capacitor Cs which decrease is involved in correcting the mobility μ is represented by ΔV in FIGS. 12A to 12E, FIG. 19, and FIG. 20.
In the pixel circuit 5, after the passage of the mobility correcting period, the writing signal WS is lowered at time t5. As a result, the pixel circuit 5 starts an emission period, and makes the organic EL element 8 emit light by the driving current Ids corresponding to the voltage across the storage capacitor Cs, as shown in FIG. 20. Incidentally, in the pixel circuit 5, after the emission period is started, the gate voltage Vg and the source voltage Vs of the driving transistor Tr2 are raised by a so-called bootstrap circuit. Vel in FIG. 20 is a voltage of an amount of the rise.
Thus, the pixel circuit 5 prepares for the process of correcting the threshold voltage of the driving transistor Tr2 in a period from time t0 to time t2 in which period the gate voltage of the driving transistor Tr2 is lowered to the voltage Vss. In a next period from time t2 to time t3, the pixel circuit 5 sets the voltage across the storage capacitor Cs to the threshold voltage Vth of the driving transistor Tr2 to correct the threshold voltage of the driving transistor Tr2. In addition, in a period from time t4 to time t5, the pixel circuit 5 corrects the mobility of the driving transistor Tr2, and samples the gradation setting voltage Vsig.
Japanese Patent Laid-Open No. 2007-133284 (hereinafter referred to as Patent Document 2) proposes a constitution in which the process of correcting a variation in the threshold voltage of the driving transistor Tr2 is divided and performed a plurality of times. According to the constitution disclosed in Patent Document 2, a sufficient time can be assigned to the correction of variation in the threshold voltage even when a time assigned to the setting of a gradation in a pixel circuit is shortened with increase in precision. Thus, even when precision is increased, degradation in image quality due to variation in the threshold voltage can be prevented.
It is therefore considered that when the method disclosed in Patent Document 2 is applied to the method disclosed in Patent Document 1, a display device capable of maintaining high image quality even when precision is increased can be obtained by a simple constitution.
FIGS. 21A, 21B, 21C, 21D, 21E, and 21F are time charts of a pixel circuit considered when the method disclosed in Patent Document 2 is applied to the method disclosed in Patent Document 1 by contrast with FIGS. 12A to 12E.
In this case, gradation setting voltages Vsig for respective pixel circuits 5 connected to the signal line DTL are output to the signal line DTL with the fixed voltage Vofs for threshold voltage correction interposed between the gradation setting voltages Vsig. In the pixel circuit 5, the writing signal WS is raised intermittently so as to correspond to the driving of the signal line DTL, and the voltage across the storage capacitor Cs is discharged via the driving transistor Tr2 in a plurality of periods. Thereby, in the example of FIGS. 21A to 21F, a variation in threshold voltage of the driving transistor Tr2 is corrected in a plurality of separate periods. Incidentally, in FIGS. 21A to 21F, VD denotes a vertical synchronizing signal.
In addition, Japanese Patent Laid-Open No. 2006-338042 (hereinafter referred to as Patent Document 3) discloses a constitution that sets the light emission luminance of an organic EL element by current driving.